Let's grow together

  • SoC Level Verification.

  • SoC verification,spec to silicon
  • Advanced tesbench solutions
  • Build test plan from scratch
  • Free TB models to customers.
  • SoC DV flow from scratch
  • Formal verification
  • Derivative SoC DV
  • Reusable TB Development
  • “C” and “SV” based testing
  • coverage driven verification.
  • Regression flow/automation
  • Gate level simulations
  • Low power verification
  • Accelerator platform based
  • Usecase driven testing
  • IP Level Verification.

  • IP TB building from Scratch
  • SV,UVM,OVM based DV
  • Test plan development
  • Coverage driven verification
  • Code
  • Statement
  • Branch…
  • Constraint random verification
  • Low power verification
  • Formal verification
  • Accelerator platform based
  • FPGA based stress testing
  • Higher level reusable flow
  • Performance testing
  • FPGA Prototyping.

  • Porting IP or SoC to FPGA
  • Building FPGA Prototyping
  • Testing on FPGA
  • Custom FPGA prototyping
  • FPGA based PCB design
  • PSOC
  • Embedded CPU based testing
  • ASIC implementation.

  • Design Implementation
  • IP Design from spec
  • RTL customization
  • IP integration
  • Low power insertions
  • ASIC synthesis
  • Logic equivalence check
  • Subsystem design
  • Low power design rule checks
  • Custom SoC/IP design
  • Design flow Development
  • Design optimization
  • IP or SoC Bug fixes
  • Legacy IP support