ASIC Design

Developing high quality RTL is challenging because the chip needs to be low on area and power consumption and at the same time provide adequate performance. To overcome this, we leverage dozens of years’ experience of our team and follow stringent design checklist. To summarize we have expertise in the below ASIC design skill:

  • Micro-Architecture
  • RTL Development
  • RTL QC Checks e.g. Lint, CDC
  • Low Power Design Implementation & Checks
  • PCIe, Ethernet, OCP, WLAN, CPU domain

Design Verification

We have the one of the strongest team in DV. Our team can execute verification from scratch of complex SoC’s and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage. We also provide silicon proven VIP for latest IP’s and provide source code and aftersales support to our customers.

  • Advanced IP & SoC Verification
  • SV-UVM Based Constrained - Random Verification
  • Verification Plan, Environment, Test Bench Development
  • Low Power Verification
  • Gate Level simulation
  • Assertion based Formal Verification
  • VIP Development and Integration
  • Palladium, Zebu & Veloce based Validation Silicon validation

FPGA based Design

Our engineers have expertise in all the leading FPGA devices such as from Xilinx, Altera, Microsemi and are up to date with latest methodology/tools to produce efficient results. We have developed RTL coding guidelines and use our ASIC verification expertise in carrying out software based verification of FPGA designs. Below are some of cases where we can help you :

  • ASIC / IP Prototyping with FPGA
  • Embedded hardware and software support
  • FPGA-to-FPGA, FPGA-to-ASIC, ASIC-to-FPGA conversion
  • Board design and bring-up
  • System Integration & Validation